Vertical color pixel sensors such as the Foveon X3® sensor produce images have a very high information content. This property is good for producing high quality still images, but generates a large amount of data per image. The requirement to transfer large amounts of data from the imaging array places restrictions on the frame rate, which is particularly limiting for recording video.
Many prior-art imaging systems employ mosaic imagers such as Bayer pattern imagers. A single “pixel” in a Bayer pattern imager is actually four pixel sensors, two green sensors, one red sensor, and one blue sensor. Two color pixels of a Bayer pattern imager are depicted in FIG. 1, a top view of a typical Bayer pattern color pixel sensor layout. A first color pixel includes red sensor 10, green sensors 12 and 14 and blue sensor 16. A second color pixel includes red sensor 18, green sensors 20 and 22 and blue sensor 24. Each color pixel occupies two adjacent rows, shown in FIG. 1 as Row i and Row (i+1). If the readout time per row is t, then the readout time for three colors in a single pixel requires reading two rows and is equal to 2t.
A simplified cross section of a color CMOS image sensor 30, such as a Foveon X3® color pixel sensor, including three horizontally aligned vertical color pixel sensors disposed at different depths in a semiconductor substrate is depicted in FIG. 2A. A blue sensor 32 is located at or near the surface of a semiconductor substrate or well. Contact is made to the blue sensor 32 via contact region 34. A green sensor 36 is located in the semiconductor substrate or well beneath and horizontally aligned with the blue sensor 32. Contact is made to the green sensor 36 via contact region 38 formed at the top of contact plug 40. A red sensor 42 is located in the semiconductor substrate or well beneath and horizontally aligned with the blue sensor 32 and the green sensor 36. Contact is made to the red sensor 42 via contact region 44 formed at the top of contact plug 46. The blue, green, and red pixel sensors are formed as photodiodes as is known in the art.
Referring now to FIG. 2B, a simplified schematic diagram of a portion of an array of pixel sensors such as the one depicted in FIG. 2A shows an illustrative prior-art row and column wiring scheme for operating the array. The array includes two rows, Row i and Row (i+1), and four columns of pixel sensors, C0, C1, C2, and C3. The pixel sensor at Row i, column C0 is identified by dashed line 50.
The individual color pixel sensors are shown as rectangles in FIG. 2B. A pixel (shown in dashed lines 50) includes a red sensor 52, a green sensor 54, and a blue sensor 56. Red sensor 52 is coupled to column line C0 (reference numeral 58) via transfer transistor 60, whose gate is driven by transfer gate line TGir at reference numeral 62. Green sensor 54 is coupled to column line C0 58 via transfer transistor 64, whose gate is driven by transfer gate line TGig at reference numeral 66. Blue sensor 56 is coupled to column line C0 58 via transfer transistor 68, whose gate is driven by transfer gate line TGib at reference numeral 70. Persons of ordinary skill in the art will appreciate that the other pixels (undesignated by reference numerals in FIG. 2B), are usually identical to pixel 50.
The readout process for the array depicted in FIG. 2B places the outputs of the red, green and blue sensors 52, 54, and 56 on the column line C0 58 one at a time by activating one of the transfer gate lines 62 (red), 66 (green), and 70 (blue). Persons of ordinary skill in the art will readily appreciate that the accumulated charge from the individual color pixel sensors in the other columns (C1, C2, and C3) of Row i will also be read out simultaneously with the accumulated charges of sensors 52, 54, and 56 as detailed above and that the pixel sensors in other rows of the array may then be read using the same operations as detailed for Row i herein. Persons of ordinary skill in the art will also readily appreciate that other steps, such as pixel reset and dark level read operations, will be involved in operation of the array, but these steps are not detailed here in order to avoid overcomplicating the disclosure and thus obscuring the invention.
The architecture shown in FIG. 2B utilizes three transfer gate lines (62, 66, and 70) per row and a single column line (e.g., C0 58) per column. Using the row readout time t of the Bayer pattern sensor example of FIG. 1, the time to read out one row of the array of FIG. 2B is 3t. These three passes are required to capture all three colors for each row. One advantage of the architecture of FIG. 2B is that is does not have color aliasing.